JPH0453000Y2 - - Google Patents

Info

Publication number
JPH0453000Y2
JPH0453000Y2 JP1986161922U JP16192286U JPH0453000Y2 JP H0453000 Y2 JPH0453000 Y2 JP H0453000Y2 JP 1986161922 U JP1986161922 U JP 1986161922U JP 16192286 U JP16192286 U JP 16192286U JP H0453000 Y2 JPH0453000 Y2 JP H0453000Y2
Authority
JP
Japan
Prior art keywords
lead
straight line
imaginary straight
main body
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1986161922U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6367257U (en]
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986161922U priority Critical patent/JPH0453000Y2/ja
Publication of JPS6367257U publication Critical patent/JPS6367257U/ja
Application granted granted Critical
Publication of JPH0453000Y2 publication Critical patent/JPH0453000Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1986161922U 1986-10-22 1986-10-22 Expired JPH0453000Y2 (en])

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986161922U JPH0453000Y2 (en]) 1986-10-22 1986-10-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986161922U JPH0453000Y2 (en]) 1986-10-22 1986-10-22

Publications (2)

Publication Number Publication Date
JPS6367257U JPS6367257U (en]) 1988-05-06
JPH0453000Y2 true JPH0453000Y2 (en]) 1992-12-14

Family

ID=31088694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986161922U Expired JPH0453000Y2 (en]) 1986-10-22 1986-10-22

Country Status (1)

Country Link
JP (1) JPH0453000Y2 (en])

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942859U (en]) * 1972-07-17 1974-04-15
JPS5252464U (en]) * 1975-10-13 1977-04-14
JPS5331968U (en]) * 1976-08-26 1978-03-18
JPS6228782Y2 (en]) * 1980-04-28 1987-07-23

Also Published As

Publication number Publication date
JPS6367257U (en]) 1988-05-06

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